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M67204H - Rad Tolerant High Speed 4Kx9 CMOS Parallel Fifo

General Description

The M67204H implements a first-in first-out algorithm, featuring asynchronous read/write operations.

The FULL and EMPTY flags prevent data overflow and underflow.

The expansion logic allows unlimited expansion in word size and depth with no timing penalties.

Key Features

  • First-in First-out Dual Port Memory.
  • 4096-bit x 9 Organization.
  • Fast Flag and Access Times: 15, 30 ns.
  • Wide Temperature Range: -55 °C to +125°C.
  • Fully Expandable by Word Width or Depth.
  • Asynchronous Read/Write Operations.
  • Empty, Full and Half Flags in Single Device Mode.
  • Retransmit Capability.
  • Bi-directional.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Features • First-in First-out Dual Port Memory • 4096-bit x 9 Organization • Fast Flag and Access Times: 15, 30 ns • Wide Temperature Range: -55 °C to +125°C • Fully Expandable by Word Width or Depth • Asynchronous Read/Write Operations • Empty, Full and Half Flags in Single Device Mode • Retransmit Capability • Bi-directional Applications • Battery Backup Operation: 2V Data Retention • TTL Compatible • Single 5V ± 10% Power Supply • No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2 www.DataSheet4U.com • Tested up to a Total Dose of 30 krads (Si) according to MIL STD 883 Method 1019 • QML Q and V with SMD 5962-89568 • ESCC B with specification 9301/049 Rad.