M67204H Datasheet | Atmel

Features - First-in First-out Dual Port Memory - 4096-bit x 9 Organization - Fast Flag and Access Times: 15, 30 ns - Wide Temperature Range: -55 °C to +125°C - Fully Expandable by Word Width or Depth - Asynchronous Read/Write Operations - Empty, Full and Half Flags in Single Device Mode - Retransmit Capability - Bi-directional Applications - Battery Backup Operation: 2V Data Retention - TTL patible - Single 5V ± 10% Power Supply - No Single Event Latch-up below a LET Threshold of 80 Me V/mg/cm2 .. - Tested up to a Total Dose of 30 krads (Si) according to MIL STD 883 Method 1019 - QML Q and V with SMD 5962-89568 - ESCC B with specification 9301/049 Rad. Tolerant High Speed 4 Kb x 9 Parallel FIFO M67204H Description The M67204H implements a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow. The expansion logic allows unlimited expansion in word size and depth with no timing penalties. Twin address pointers automatically generate internal read and write addresses, and no external address information is required for the Atmel FIFOs. address pointers are automatically incremented with the write pin and read pin. The 9 bits wide data are used in data munications applications where a parity bit for error checking is necessary. The retransmit pin reset the read pointer to zero without affecting the write pointer. This is very useful for retransmitting data when an error is detected in the system. Using an array of eight transistors (8T) memory cell, the M67204H bines an extremely low standby supply current (typ = 0.1 µA) with a fast access time at 15 ns over the full temperature range. All versions offer battery backup data retention capability with a typical power consumption at less than 2 µW. The M67204H is processed according to the methods of the latest revision of the MIL PRF 38535 (Q and V) or ESA SCC 9000. 4141I- AERO- 06/04 Block Diagram .. Pin Configuration DIL ceramic...