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Main Features
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8-bit Resolution 500 Msps (min) Sampling Rate Power Consumption: 3.8W Typ 500 mVpp Differential or Single-ended Analog Inputs Differential or Single-ended 50Ω ECL Compatible Clock Inputs ECL or LVDS/HSTL Output Compatibility ADC Gain Adjust Data Ready Output with Asynchronous Reset Gray or Binary Selectable Output Data; NRZ Output Mode Enhanced CBGA Package with Ceramic Lid Evaluation Board: TSEV8308500GL (Detailed Specification on Request) Demultiplexer TS81102G0: Companion Device Available
ADC 8-bit 500 Msps TS8308500
Performance
• 1.3 GHz Full Power Input Bandwidth • Band Flatness: 0.5 dB up to 500 MHz • SINAD = 45 dB (7.2 Effective Bits), SFDR = 54 dBc
at FS = 500 Msps, FIN = 20 MHz
• SINAD = 43 dB (7.