TS8388B Datasheet | Atmel

.. Features - - - - - - - - - - - - - - - - - - - - - 8-bit Resolution ADC Gain Adjust 1.5 GHz Full Power Input Bandwidth (-3 d B) 1 GSPS (min) Sampling Rate SINAD = 44.3 d B (7.2 Effective Bits), SFDR = 58 d Bc, at FS = 1 GSPS, FIN = 20 MHz SINAD = 42.9 d B (7.0 Effective Bits), SFDR = 52 d Bc, at FS = 1 GSPS, FIN = 500 MHz SINAD = 40.3 d B (6.8 Effective Bits), SFDR = 50 d Bc, at FS = 1 GSPS, FIN = 1000 MHz (-3 d B FS) 2-tone IMD: -52 d Bc (489 MHz, 490 MHz) at 1 GSPS DNL = 0.3 lsb, INL = 0.7 lsb Low Bit Error Rate (10-13) at 1 GSPS Very Low Input Capacitance: 3 p F 500 m Vpp Differential or Single-ended Analog Inputs Differential or Single-ended 50Ω ECL patible Clock Inputs ECL or LVDS/HSTL Output patibility Data Ready Output with Asynchronous Reset Gray or Binary Selectable Output Data; NRZ Output Mode Power Consumption: 3.4W at Tj = 70°C Typical Radiation Tolerance Oriented Design (150 Krad (Si) measured) Two Package Versions Evaluation board: TSEV8388B Demultiplexer TS81102G0: panion Device Available ADC 8-bit 1 GSPS TS8388B Applications - - - - Digital Sampling Oscilloscopes Satellite Receiver Electronic Countermeasures/Electronic Warfare Direct RF Down-conversion Description The TS8388B is a monolithic 8-bit analog-to-digital converter, designed for digitizing wide bandwidth analog signals at very high sampling rates of up to 1 GSPS. The TS8388B uses an innovative architecture, including an on-chip Sample and Hold (S/H), and is fabricated with an advanced high speed bipolar process. The on-chip S/H has a 1.5 GHz full power input bandwidth, providing excellent dynamic performance in undersampling applications (High IF digitizing). Rev. 2144C- BDC- 04/03 Functional Description Block Diagram The following figure shows the simplified block diagram. Figure 1. Simplified Block Diagram GAIN MASTER/SLAVE TRACK & HOLD AMPLIFIER VIN, VINB G=2 T/H G=1 T/H G=1 RESISTOR CHAIN ANALOG ENCODING BLOCK 4 INTERPOLATION STAGES 4 5 REGENERATION LATCHES...