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TSC695F - Rad-Hard 32-bit SPARC Embedded Processor

General Description

The TSC695F (ERC32 Single-Chip) is a highly integrated, high-performance 32-bit RISC embedded processor implementing the SPARC architecture V7 specification.

Key Features

  • Integer Unit Based on SPARC V7 High-performance RISC Architecture.
  • Optimized Integrated 32/64-bit Floating-point Unit.
  • On-chip Peripherals.
  • EDAC and Parity Generator and Checker.
  • Memory Interface Chip Select Generator Waitstate Generation Memory Protection.
  • DMA Arbiter.
  • Timers General Purpose Timer (GPT) Real-time Clock Timer (RTCT) Watchdog Timer (WDT) www. DataSheet4U. com.
  • Interrupt Controller with 5 External Inputs.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Features • Integer Unit Based on SPARC V7 High-performance RISC Architecture • Optimized Integrated 32/64-bit Floating-point Unit • On-chip Peripherals – EDAC and Parity Generator and Checker – Memory Interface Chip Select Generator Waitstate Generation Memory Protection – DMA Arbiter – Timers General Purpose Timer (GPT) Real-time Clock Timer (RTCT) Watchdog Timer (WDT) www.DataSheet4U.com – Interrupt Controller with 5 External Inputs – General Purpose Interface (GPI) – Dual UART • Speed Optimized Code RAM Interface 8- or 40-bit boot-PROM (Flash) Interface • IEEE 1149.1 Test Access Port (TAP) for Debugging and Test Purposes • Fully Static Design • Performance: 12 MIPs/3 MFlops (Double Precision) at SYSCLK = 15 MHz • Core Consumption: 1.0W Typ. at 20 MIPs/0.7W typ.