AT89C5131A-L
Overview
- 80C52X2 Core (6 Clocks per Instruction) - Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode - Dual Data Pointer - Full-duplex Enhanced UART (EUART) - Three 16-bit Timer/Counters: T0, T1 and T2 - 256 Bytes of Scratchpad RAM
- 16/32-Kbyte On-chip Flash EEPROM In-System Programming through USB - Byte and Page (128 bytes) Erase and Write - 100k Write Cycles
- 3-KbyteFlash EEPROM for Bootloader - Byte and Page (128 bytes) Erase and Write - 100k Write Cycles
- 1-Kbyte EEPROM Data ( - Byte and Page (128 bytes) Erase and Write - 100k Write Cycles
- On-chip Expanded RAM (ERAM): 1024 Bytes
- Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
- USB 1.1 and 2.0 Full Speed Compliant Module with Interrupt on Transfer Completion - Endpoint 0 for Control Transfers: 32-byte FIFO - 6 Programmable Endpoints with In or Out Directions and with Bulk, Interrupt or Isochronous Transfers
- Endpoint 1, 2, 3: 32-byte FIFO
- Endpoint 4, 5: 2 x 64-byte FIFO with Double Buffering (Ping-pong Mode)
- Endpoint 6: 2 x 512-byte FIFO with Double Buffering (Ping-pong Mode) - Suspend/Resume Interrupts - Power-on Reset and USB Bus Reset - 48 MHz DPLL for Full-speed Bus Operation - USB Bus Disconnection on Microcontroller Request
