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ATU18 - 0.18um ULC

Description

The ATU18 series of ULCs are fully suited for conversion of latest CPLDs and FPGAs.

It supports within one ULC 55Kbits to 847Kbits DPRAM and 45Kgates to 1000 Kgates.

Typically, ULC die size is 50% smaller than the equivalent FPGA.

Features

  • High Performance ULC Family Suitable for Latest CPLDs and FPGAs conversion Very effective associated Physical synthesis/optimization Flow From 45K Gates up to 1000K Gates Supported From 55Kbit to 847Kbit DPRAM Compatible with Xilinx and Altera Latest FPGA’s Pin-count: Over 700 pins VDD 1.8V +/- 0.15V for core.

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com Features • • • • • • • • • • • • • • • • • • • High Performance ULC Family Suitable for Latest CPLDs and FPGAs conversion Very effective associated Physical synthesis/optimization Flow From 45K Gates up to 1000K Gates Supported From 55Kbit to 847Kbit DPRAM Compatible with Xilinx and Altera Latest FPGA’s Pin-count: Over 700 pins VDD 1.8V +/- 0.15V for core; 1.8V, 2.5V, 3.3V for Periphery Any Pin–out Matched Full Range of Packages: PQFP/TQFP/VQFP, BGA/FLBGA, PGA/PPGA, QFN, CS Available in Commercial, Industrial and Military Grades 0.
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