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TSPC106 - PCI Bus Bridge Memory Controller

General Description

The TSPC106 provides an integrated, high-bandwidth, high-performance, TTL-compa

Key Features

  • Processor Bus Frequency Up to 66 MHz and 83.3 MHz.
  • 64-bit Data Bus and 32-bit Address Bus.
  • L2 Cache Control for 256-Kbyte, 512-Kbyte, 1-Mbyte Sizes.
  • Provides Support for Either Asynchronous SRAM, Burst SRAM or Pipelined Burst SRAM.
  • Compliant with PCI Specification, Revision 2.1.
  • PCI Interface Operates at 20 to 33 MHz, 3.3V/5.0V-compatible.
  • IEEE 1149.1-compliant, JTAG Boundary-scan Interface.
  • PD Max = 1.7 Watts (66 MHz), Ful.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Features • Processor Bus Frequency Up to 66 MHz and 83.3 MHz • 64-bit Data Bus and 32-bit Address Bus • L2 Cache Control for 256-Kbyte, 512-Kbyte, 1-Mbyte Sizes • Provides Support for Either Asynchronous SRAM, Burst SRAM or Pipelined Burst SRAM • Compliant with PCI Specification, Revision 2.1 • PCI Interface Operates at 20 to 33 MHz, 3.3V/5.0V-compatible • IEEE 1149.1-compliant, JTAG Boundary-scan Interface • PD Max = 1.7 Watts (66 MHz), Full Operating Conditions • Nap, Doze and Sleep Modes Reduce Power Consumption • Fully Compliant with MIL-STD-883 Class Q or According to Atmel Standards • Upscreenings Based on Atmel Standards • Full Military Temperature Range (-55°C ≤ Tj ≤ +125°C) – Industrial Temperature Range (-40°C ≤ Tj ≤ +110°C) • VCC = 3.