A101VW01-V3 Description
Remark 2 STVD I/O Vertical start pulse signal input or output Note 1 3 OE I Output enable. The gate driver outputs are disable when OE = “H”. 4 CKV I Vertical clock 5 STVU I/O Vertical start pulse signal input or output Note 1 6 GND P Power ground 7 EDGSL Select raising edge or raising/falling edge I When EDGSL = "0", Latching source data.