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AX1250ES - 2A Sink/Source Bus Termination Regulator

General Description

The AX1250ES is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc.

devices requirements.

Key Features

  • include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. The AX1250ES are available in the SOP-8L-EP (Exposed Pad) surface mount packages. .

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Datasheet Details

Part number AX1250ES
Manufacturer AXElite
File Size 653.14 KB
Description 2A Sink/Source Bus Termination Regulator
Datasheet download datasheet AX1250ES Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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AX1250ES 2A Sink/Source Bus Termination Regulator  GENERAL DESCRIPTION The AX1250ES is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requirements. The regulator is capable of actively sinking or sourcing up to 2A while regulating an output voltage to within 40mV. The output termination voltage cab be tightly regulated to track 1/2VDDQ by two external voltage divider resistors or the desired output voltage can be programmed by externally forcing the REFEN pin voltage.