AX1250ES Overview
Description
The AX1250ES is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requirements.
Key Features
- The AX1250ES are available in the SOP-8L-EP (Exposed Pad) surface mount packages
- High Accuracy Output Voltage at Full-Load Output Voltage traces REFEN Pin Voltage
- 1/9 Axelite Confidential Materials, do not copy or distribute without written consent
- Rev.1.3 Aug.24, 2011 AX1250ES
