ASFLMX-50.000MHz-5ABB Datasheet PDF (Ultra-Low Phase Jitter LVDS SMD Clock Oscillator)

ASFLMX-50.000MHz-5ABB - Ultra-Low Phase Jitter LVDS SMD Clock Oscillator

Description

2 Faraday, Suite# B | Irvine | CA 92618 Revised: 04.15.15 Ph.

949.546.8000 | Fax.

Features

50MHz LVDS.
Typical phase noise: 121fs (Integration range: 1.875MHz-20MHz).
±50ppm total frequency stability over -40°C to +85°C temperature range.
Industry standard 6-Pin 5 x 3.2mm LGA package Pb RoHS/RoHS II compliant 5.0 x 3.2 x 1.4mm.

Datasheet Details

Part number	ASFLMX-50.000MHz-5ABB
Manufacturer	Abracon
File Size	8.86 MB
Description	Ultra-Low Phase Jitter LVDS SMD Clock Oscillator
Datasheet	ASFLMX-50.000MHz-5ABB Datasheet
Additional preview pages of the ASFLMX-50.000MHz-5ABB datasheet.

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Full PDF Text Transcription

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Ultra-Low Phase Jitter LVDS SMD Clock Oscillator ASFLMX-50.000MHz-5ABB ESD Sensitive Moisture Sensitivity Level – MSL 3 FEATURES: • 50MHz LVDS • Typical phase noise: 121fs (Integration range: 1.875MHz-20MHz) • ±50ppm total frequency stability over -40°C to +85°C temperature range • Industry standard 6-Pin 5 x 3.2mm LGA package Pb RoHS/RoHS II compliant 5.0 x 3.2 x 1.4mm APPLICATIONS: • Communications • Backplane reference clock • SERDES reference clock • FPGA High Performance KEY ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Item Minimum Maximum Unit Condition Supply Voltage -0.3 +3.6 V Storage Temp. Lead Temp.(soldering, 10s) -55 +125 +260 °C °C ESD (HBM) 2 kV VDD = 2.375 - 3.63V, TA = -40°C to +85°C, outputs terminated with 100 Ohms between Q and /Q.

Published: Oct 24, 2019 |