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v1.0
ProASIC3E Flash Family FPGAs
with Optional Soft ARM® Support Features and Benefits
High Capacity
• 600 k to 3 Million System Gates • 108 to 504 kbits of True Dual-Port SRAM • Up to 620 User I/Os
®
Reprogrammable Flash Technology
• • • • 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process Live at Power-Up (LAPU) Level 0 Support Single-Chip Solution Retains Programmed Design when Powered Off
On-Chip User Nonvolatile Memory
• 1 kbit of FlashROM with Synchronous Interfacing
High Performance
• 350 MHz System Performance • 3.3 V, 66 MHz 64-Bit PCI
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant) • FlashLock® to Secure FPGA Contents
• 1.5 V, 1.8 V, 2.5 V, and 3.
A3PE600 Datasheet
