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AX250 - Axcelerator Family FPGAs

Datasheet Summary

Description

Device Architecture 1-1 Programmable Interconnect Element

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Features

  • Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2.
  • Registered I/Os.
  • Hot-Swap Compliant I/Os (except PCI).
  • Programmable Slew Rate and Drive Strength on Outputs.
  • Programmable Delay and Weak Pull-Up/Pull-Down Circuits on Inputs Embedded Memory:.
  • Variable-Aspect 4,608-bit RAM Blocks (x1, x2, x4, x9,.

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Datasheet preview – AX250

Datasheet Details

Part number AX250
Manufacturer Actel
File Size 2.40 MB
Description Axcelerator Family FPGAs
Datasheet download datasheet AX250 Datasheet
Additional preview pages of the AX250 datasheet.

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Full PDF Text Transcription

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v2.7 Axcelerator Family FPGAs u e ™ Leading-Edge Performance • • • • • • • • • 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Up to 2 Million Equivalent System Gates Up to 684 I/Os Up to 10,752 Dedicated Flip-Flops Up to 295 kbits Embedded SRAM/FIFO Manufactured on Advanced 0.15 μm CMOS Antifuse Process Technology, 7 Layers of Metal Single-Chip, Nonvolatile Solution Up to 100% Resource Utilization with 100% Pin Locking 1.5V Core Voltage for Low Power Footprint Compatible Packaging Flexible, Multi-Standard I/Os: – 1.5V, 1.8V, 2.5V, 3.3V Mixed Voltage Operation – Bank-Selectable I/Os – 8 Banks per Chip – Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3V PCI, and 3.
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