EX256 Datasheet | Actel

v4.2 eX Family FPGAs FuseLock Leading Edge Performance - - - 240 MHz System Performance 350 MHz Internal Performance 3.9 ns Clock-to-Out (Pad-to-Pad) - - - - - - Specifications - - - - 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops (Using CC Macros) 0.22µm CMOS Process Technology Up to 132 User-Programmable I/O Pins - - - - - Features - - - - - - High-Performance, Low-Power Antifuse FPGA LP/Sleep Mode for Additional Power Savings Advanced Small-Footprint Packages Hot-Swap pliant I/Os Single-Chip Solution Nonvolatile Live on Power-Up No Power-Up/Down Sequence Required for Supply Voltages Configurable Weak-Resistor Pull-Up or Pull-Down for Tristated Outputs during...