Datasheet Summary
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FINAL
’L: H-7/10/15/20
IND: H-10/15/20
PALCE26V12 Family
28-Pin EE CMOS Versatile PAL Device
DISTINCTIVE CHARACTERISTICS s 28-pin versatile PAL programmable logic device architecture s Electrically erasable CMOS technology provides half power (only 115 mA) at high speed (7.5 ns propagation delay) s 14 dedicated inputs and 12 input/output macrocells for architectural flexibility s Macrocells can be registered or binatorial, and active high or active low s Varied product term distribution allows up to 16 product terms per output s Two clock inputs for independent functions s Global asynchronous reset and synchronous preset for initialization s Register preload...