UT8SP2M48 Datasheet PDF - Aeroflex Circuit Technology 96Megabit Pipelined SSRAM Specs

UT8SP2M48 - 96Megabit Pipelined SSRAM

Datasheet Summary

Description

Chip Enable 0, Input, Active LOW: Sampled on the rising edge of CLK.

Used in conjunction with CS1 and CS2 to select or deselect the device.

Chip Enable 1 Input, Active HIGH: Sampled on the rising edge of CLK.

Features

 Synchronous SRAM organized as 2Meg words x 48bit  Continuous Data Transfer (CDT) architecture eliminates wait states between read and write operations  Supports 40MHz to 133MHz bus operations  Internally self-timed output buffer control eliminates the need for synchronous output enable  Registered inputs and outputs for pipelined operation  Single 2.5V to 3.3V supply  Clock-to-output time - Clk to Q = 7ns  Clock Enable (CEN) pin to enable clock and suspend operation  Synchronous self-t.

Datasheet Details

Part number	UT8SP2M48
Manufacturer	Aeroflex Circuit Technology
File Size	323.13 KB
Description	96Megabit Pipelined SSRAM
Datasheet	UT8SP2M48 Datasheet
Additional preview pages of the UT8SP2M48 datasheet.

📁 Similar Datasheet

UT8005 - 8A High Power Ultra Fast Rectifiers (CITC)

UT801 - 8A High Power Ultra Fast Rectifiers (CITC)

UT802 - 8A High Power Ultra Fast Rectifiers (CITC)

UT804 - 8A High Power Ultra Fast Rectifiers (CITC)

UT806 - 8A High Power Ultra Fast Rectifiers (CITC)

UT8067 - N-CHANNEL MOSFET (UTC)

UT808 - 8A High Power Ultra Fast Rectifiers (CITC)

UT80CRH196KD - 20MHz 16-bit Microcontroller (AEROFLEX)

UT80N04 - N-CHANNEL MOSFET (UTC)

UT80P06 - P-CHANNEL POWER MOSFET (UTC)

Full PDF Text Transcription

Click to expand full text

Standard Products UT8SP2M48 96Megabit Pipelined SSRAM Preliminary Datasheet www.aeroflex.com/memories April 2015 FEATURES  Synchronous SRAM organized as 2Meg words x 48bit  Continuous Data Transfer (CDT) architecture eliminates wait states between read and write operations  Supports 40MHz to 133MHz bus operations  Internally self-timed output buffer control eliminates the need for synchronous output enable  Registered inputs and outputs for pipelined operation  Single 2.5V to 3.

Published: Oct 4, 2016 |