UT8SP2M48 Datasheet | Aeroflex Circuit Technology

Standard Products UT8SP2M48 96Megabit Pipelined SSRAM Preliminary Datasheet .aeroflex./memories April 2015 Features  Synchronous SRAM organized as 2Meg words x 48bit  Continuous Data Transfer (CDT) architecture eliminates wait states between read and write operations  Supports 40MHz to 133MHz bus operations  Internally self-timed output buffer control eliminates the need for synchronous output enable  Registered inputs and outputs for pipelined operation  Single 2.5V to 3.3V supply  Clock-to-output time - Clk to Q = 7ns  Clock Enable (CEN) pin to enable clock and suspend operation  Synchronous self-timed writes  Three Chip Enables (CS0, CS1, CS2) for simple depth expansion...