UT54ACS74 Description
The UT54ACS74 and the UT54ACTS74 contain two independent D-type positive triggered flip-flops. A low level at the Preset or Clear inputs sets or resets the outputs regardless of the levels of the other inputs. When Preset and Clear are inactive (high), data at the D input meeting the setup time requirement CLR1 is transferred to the outputs on the positive-going edge of the D1 clock pulse.
UT54ACS74 Key Features
- radiation-hardened CMOS
- Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package
- 14-pin DIP
- 14-lead flatpack