T8105 Datasheet | Agere Systems

Features s s s s Fully patible to the T8100, T8100A, and T8102. H.100/H.110 pliant interface; all mandatory signals. Programmable connections to any of the 4096 time slots on the H.100/H.110 bus. Programmable switching between local time slots and H.100/H.110 bus, up to 512 connections. s Refer to website .agere./ambassador for additional information. µP AGERE T8105 H.100/H.110 BUS H.100/H.110 BUS INTERFACE MICROPROCESSOR INTERFACE 512 H-BUS 1024 L-BUS TIME-SLOT SWITCH DSP . . . DSP s s s s Up to 16 local serial inputs and 16 local serial outputs, (2, 4, and 8 Mbits/s). Microprocessor interface: Intel †/Motorola‡ modes. Choice of frame integrity or minimum latency switching on a per-time-slot basis: - Frame integrity to ensure proper switching of wideband data. - Minimum latency switching to reduce delay in voice channels. Subrate switching of 1 bit, 2 bits, and 4 bits. Two independently programmable groups of up to 12 framing signals each. Programmable GPIO. On-chip phase-locked loop (PLL) for H.100/H.110, MVIP, or Dialogic’s- SC-bus clock operation in master or slave clock modes. s s LOCAL TDM INTERFACE Programmable switching between local time slots,...