Description
The A6812 device combines a 20-bit CMOS shift register, accompanying data latches and control circuitry with bipolar sourcing outputs ,and PNP active pull-downs.
Features
- Controlled output slew rate.
- High-speed data storage.
- 60 V minimum output break down.
- High data-input rate.
- PNP active pull-downs.
- Low output-saturation voltages.
- Low-power CMOS logic and latches.
- Improved replacements for TL5812x, UCN5812x, and
UCQ5812x
Package:
28-pin SOICW (Package LW)
Not to scale
28-pin PLCC (EP package).
A6812 Datasheet
