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AS7C251MPFD18A - 2.5V 1M x 18 pipelined burst synchronous SRAM

Description

The AS7C251MPFD18A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized as 1,048,576 words X 18 bits and incorporates a two-stage register-register pipeline for highest frequency on any given technology.

Features

  • Organization: 1,048,576 x18 bits Fast clock speeds to 166 MHz Fast clock to data access: 3.5/3.8 ns Fast OE access time: 3.5/3.8 ns Fully synchronous register-to-register operation Double-cycle deselect Asynchronous output enable control Available 100-pin TQFP package.
  • Individual byte write and global write Multiple chip enables for easy expansion 2.5V core p.

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Datasheet preview – AS7C251MPFD18A

Datasheet Details

Part number AS7C251MPFD18A
Manufacturer Alliance Semiconductor Corporation
File Size 555.56 KB
Description 2.5V 1M x 18 pipelined burst synchronous SRAM
Datasheet download datasheet AS7C251MPFD18A Datasheet
Additional preview pages of the AS7C251MPFD18A datasheet.

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Other Datasheets by Alliance Semiconductor Corporation
  • AS7C251MPFD32A - (AS7C251MPFD32A / AS7C251MPFD36A) 2.5V 1M x 32/36 pipelined burst synchronous SRAM
  • AS7C251MPFD36A - (AS7C251MPFD32A / AS7C251MPFD36A) 2.5V 1M x 32/36 pipelined burst synchronous SRAM
  • AS7C251MPFS18A - 2.5V 1M x 18 pipelined burst synchronous SRAM
  • AS7C251MPFS32A - (AS7C251MPFS32A / AS7C251MPFS36A) 2.5V 1M x 32/36 pipelined burst synchronous SRAM
  • AS7C251MPFS36A - (AS7C251MPFS32A / AS7C251MPFS36A) 2.5V 1M x 32/36 pipelined burst synchronous SRAM
  • AS7C251MFT18A - 2.5V 1M x 18 flowthrough burst synchronous SRAM
  • AS7C251MFT32A - (AS7C251MFT32A / AS7C251MFT36A) 2.5V 1M x 32/36 Flow-through synchronous SRAM
  • AS7C251MFT36A - (AS7C251MFT32A / AS7C251MFT36A) 2.5V 1M x 32/36 Flow-through synchronous SRAM

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February 2005 ® AS7C251MPFD18A 2.5V 1M x 18 pipelined burst synchronous SRAM Features • • • • • • • • Organization: 1,048,576 x18 bits Fast clock speeds to 166 MHz Fast clock to data access: 3.5/3.8 ns Fast OE access time: 3.5/3.8 ns Fully synchronous register-to-register operation Double-cycle deselect Asynchronous output enable control Available 100-pin TQFP package • • • • • • Individual byte write and global write Multiple chip enables for easy expansion 2.5V core power supply Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs www.DataSheet4U.
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