AS7C251MPFD18A Datasheet | Alliance Semiconductor Corporation

Features - - - - - - - - Organization: 1,048,576 x18 bits Fast clock speeds to 166 MHz Fast clock to data access: 3.5/3.8 ns Fast OE access time: 3.5/3.8 ns Fully synchronous register-to-register operation Double-cycle deselect Asynchronous output enable control Available 100-pin TQFP package - - - - - - Individual byte write and global write Multiple chip enables for easy expansion 2.5V core power supply Linear or interleaved burst control Snooze mode for reduced power-standby mon data inputs and data outputs .. Logic block diagram CLK ADV ADSC ADSP A[19:0] CLK CS CLR Burst logic 20 18 20 Q D CS Address 1M x 18 Memory array 18 18 register GWE BWb BWE BWa CE0 CE1 CE2 D DQb CLK D DQa Q Byte Write registers Byte Write registers CLK D CE CLK D ZZ Enable register Output registers Input registers Power down Enable delay register CLK OE DQ[a,b] Selection guide -166 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 6 166 3.5 290 85 40 -133 7.5 133 3.8 270 75 40 Units ns MHz ns m A m A m...