AS7C251MPFS32A - (AS7C251MPFS32A / AS7C251MPFS36A) 2.5V 1M x 32/36 pipelined burst synchronous SRAM

Description

The AS7C251MPFS32A/36A is a high-performance CMOS 32-Mbit synchronous Static Random Access Memory (SRAM) device organized as 1,048,576 words x 32/36.

It incorporates a two-stage register-register pipeline for highest frequency on any given technology.

Features

Organization: 1,048,576 words × 32 or 36 bits.
Fast clock speeds to 200 MHz.
Fast clock to data access: 3.1/3.5/3.8 ns.
Fast OE access time: 3.1/3.5/3.8 ns.
Fully synchronous register-to-register operation.
Single-cycle deselect.
Asynchronous output enable control.
Available in 100-pin TQFP package www. DataSheet4U. com.
Individual byte write and global write Multiple.

Alliance Semiconductor Corporation

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Datasheet Details

Part number	AS7C251MPFS32A
Manufacturer	Alliance Semiconductor Corporation
File Size	568.48 KB
Description	(AS7C251MPFS32A / AS7C251MPFS36A) 2.5V 1M x 32/36 pipelined burst synchronous SRAM
Datasheet	AS7C251MPFS32A Datasheet
Additional preview pages of the AS7C251MPFS32A datasheet.

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Other Datasheets by Alliance Semiconductor Corporation

AS7C251MPFS36A - (AS7C251MPFS32A / AS7C251MPFS36A) 2.5V 1M x 32/36 pipelined burst synchronous SRAM
AS7C251MPFS18A - 2.5V 1M x 18 pipelined burst synchronous SRAM
AS7C251MPFD18A - 2.5V 1M x 18 pipelined burst synchronous SRAM
AS7C251MPFD32A - (AS7C251MPFD32A / AS7C251MPFD36A) 2.5V 1M x 32/36 pipelined burst synchronous SRAM
AS7C251MPFD36A - (AS7C251MPFD32A / AS7C251MPFD36A) 2.5V 1M x 32/36 pipelined burst synchronous SRAM
AS7C251MFT18A - 2.5V 1M x 18 flowthrough burst synchronous SRAM
AS7C251MFT32A - (AS7C251MFT32A / AS7C251MFT36A) 2.5V 1M x 32/36 Flow-through synchronous SRAM
AS7C251MFT36A - (AS7C251MFT32A / AS7C251MFT36A) 2.5V 1M x 32/36 Flow-through synchronous SRAM

Full PDF Text Transcription

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February 2005 ® AS7C251MPFS32A AS7C251MPFS36A 2.5V 1M × 32/36 pipelined burst synchronous SRAM Features • Organization: 1,048,576 words × 32 or 36 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.1/3.5/3.8 ns • Fast OE access time: 3.1/3.5/3.8 ns • Fully synchronous register-to-register operation • Single-cycle deselect • Asynchronous output enable control • Available in 100-pin TQFP package www.DataSheet4U.com • • • • • • Individual byte write and global write Multiple chip enables for easy expansion 2.

Published: Nov 17, 2008 |