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AS7C33128NTD18B - 3.3V 128Kx18 Pipelined SRAM

General Description

The AS7C33128NTD18B family is a high performance CMOS 2 Mbit synchronous Static Random Access Memory (SRAM) organized as 131,072 words × 18 bits and incorporates a LATE LATE Write.

Key Features

  • Organization: 131,072 words × 18 bits.
  • NTD™ architecture for efficient bus operation.
  • Fast clock speeds to 200 MHz.
  • Fast clock to data access: 3.0/3.5/4.0 ns.
  • Fast OE access time: 3.0/3.5/4.0 ns.
  • Fully synchronous operation.
  • Asynchronous output enable control.
  • Available in 100-pin TQFP package www. DataSheet4U. com.
  • Byte write enables.
  • Clock enable for operation hold Logic block diagram A[16:0] 17 D.

📥 Download Datasheet

Datasheet Details

Part number AS7C33128NTD18B
Manufacturer Alliance Semiconductor Corporation
File Size 489.68 KB
Description 3.3V 128Kx18 Pipelined SRAM
Datasheet download datasheet AS7C33128NTD18B Datasheet

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Other Datasheets by Alliance Semiconductor Corporation

Part Number Description
AS7C33128NTD32B (AS7C33128NTD32B / AS7C33128NTD36B) 3.3V 128Kx32/36 Pipelined SRAM
AS7C33128NTD36B (AS7C33128NTD32B / AS7C33128NTD36B) 3.3V 128Kx32/36 Pipelined SRAM
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AS7C33128NTF32B (AS7C33128NTF32B / AS7C33128NTF36B) 3.3V 128K x 32/36 Flowthrough Synchronous SRAM
AS7C33128NTF36B (AS7C33128NTF32B / AS7C33128NTF36B) 3.3V 128K x 32/36 Flowthrough Synchronous SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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April 2005 ® AS7C33128NTD18B 3.3V 128K×18 Pipelined SRAM with NTDTM Features • Organization: 131,072 words × 18 bits • NTD™ architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous operation • Asynchronous output enable control • Available in 100-pin TQFP package www.DataSheet4U.com • Byte write enables • Clock enable for operation hold Logic block diagram A[16:0] 17 D • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • Self-timed write cycles • Interleaved or linear burst modes • Snooze mode for standby operation Address register Burst logic Q 17 17 Write delay addr.