Description
The AS7C33128NTD18B family is a high performance CMOS 2 Mbit synchronous Static Random Access Memory (SRAM) organized as 131,072 words × 18 bits and incorporates a LATE LATE Write.
Features
- Organization: 131,072 words × 18 bits.
- NTD™ architecture for efficient bus operation.
- Fast clock speeds to 200 MHz.
- Fast clock to data access: 3.0/3.5/4.0 ns.
- Fast OE access time: 3.0/3.5/4.0 ns.
- Fully synchronous operation.
- Asynchronous output enable control.
- Available in 100-pin TQFP package www. DataSheet4U. com.
- Byte write enables.
- Clock enable for operation hold Logic block diagram
A[16:0] 17
D.
AS7C33128NTD18B Datasheet
