Datasheet Summary
February 2005
®
AS7C33128NTD32B AS7C33128NTD36B
3.3V 128K×32/36 Pipelined SRAM with NTDTM
Features
- Organization: 131,072 words × 32 or 36 bits
- NTD™ architecture for efficient bus operation
- Fast clock speeds to 200 MHz
- Fast clock to data access: 3.0/3.5/4.0 ns
- Fast OE access time: 3.0/3.5/4.0 ns
- Fully synchronous operation
- Asynchronous output enable control
- Available in 100-pin TQFP package ..
- Byte write enables
- Clock enable for operation hold
- Multiple chip enables for easy expansion
- 3.3V core power supply
- 2.5V or 3.3V I/O operation with separate VDDQ
- Self-timed write cycles
- Interleaved or linear burst modes
- Snooze mode for reduced power...
