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AS7C33128PFS32A - (AS7C33128PFS32A / AS7C33128PFS36A) 3.3V 128K X 32/36 pipeline burst synchronous SRAM

Description

The AS7C33128PFS32A and AS7C33128PFS36A are high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) devices organized as 131,072 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any given technology.

Features

  • Organization: 131,072 words × 32 or 36 bits.
  • Fast clock speeds to 200 MHz in LVTTL/LVCMOS.
  • Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns.
  • Fast OE access time: 3.0/3.1/3.5/4.0/5.0 ns.
  • Fully synchronous register-to-register operation.
  • Single register “Flow-through” mode.
  • Single-cycle deselect.
  • Dual-cycle deselect also available (AS7C33128PFD32A/ www. DataSheet4U. com AS7C33128PFD36A).
  • Pentium®1 compatible architect.

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Datasheet preview – AS7C33128PFS32A

Datasheet Details

Part number AS7C33128PFS32A
Manufacturer Alliance Semiconductor Corporation
File Size 378.04 KB
Description (AS7C33128PFS32A / AS7C33128PFS36A) 3.3V 128K X 32/36 pipeline burst synchronous SRAM
Datasheet download datasheet AS7C33128PFS32A Datasheet
Additional preview pages of the AS7C33128PFS32A datasheet.

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Other Datasheets by Alliance Semiconductor Corporation
  • AS7C33128PFS32B - (AS7C33128PFS32B / AS7C33128PFS36B) 3.3V 128K X 32/36 pipeline burst synchronous SRAM
  • AS7C33128PFS36A - (AS7C33128PFS32A / AS7C33128PFS36A) 3.3V 128K X 32/36 pipeline burst synchronous SRAM
  • AS7C33128PFS36B - (AS7C33128PFS32B / AS7C33128PFS36B) 3.3V 128K X 32/36 pipeline burst synchronous SRAM
  • AS7C33128PFS18B - 3.3V 128K x 18 pipeline burst synchronous SRAM
  • AS7C33128PFD18B - 3.3V 128K x 18 pipeline burst synchronous SRAM
  • AS7C33128PFD32A - (AS7C33128PFD32A / AS7C33128PFD36A) 3.3V 128K X 32/36 pipeline burst synchronous SRAM
  • AS7C33128PFD32B - (AS7C33128PFD32B / AS7C33128PFD36B) 3.3V 128K X 32/36 pipeline burst synchronous SRAM
  • AS7C33128PFD36A - (AS7C33128PFD32A / AS7C33128PFD36A) 3.3V 128K X 32/36 pipeline burst synchronous SRAM

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March 2002 ® AS7C33128PFS32A AS7C33128PFS36A 3.3V 128K X 32/36 pipeline burst synchronous SRAM Features • Organization: 131,072 words × 32 or 36 bits • Fast clock speeds to 200 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns • Fast OE access time: 3.0/3.1/3.5/4.0/5.0 ns • Fully synchronous register-to-register operation • Single register “Flow-through” mode • Single-cycle deselect • Dual-cycle deselect also available (AS7C33128PFD32A/ www.DataSheet4U.com AS7C33128PFD36A) • Pentium®1 compatible architecture and timing • Asynchronous output enable control • • • • • • • Economical 100-pin TQFP package Byte write enables Multiple chip enables for easy expansion 3.3 core power supply 2.5V or 3.
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