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AS7C33512NTD18A - 3.3V 512K x 18 Pipelined burst Synchronous SRAM

General Description

The AS7C33512NTD18A family is a high performance CMOS 8 Mbit synchronous Static Random Access Memory (SRAM) organized as 524,288 words × 18 bits and incorporates a LATE LATE Write.

Key Features

  • Organization: 524,288 words × 18 bits.
  • NTD™ architecture for efficient bus operation.
  • Fast clock speeds to 166 MHz.
  • Fast clock to data access: 3.5/4.0 ns.
  • Fast OE access time: 3.5/4.0 ns.
  • Fully synchronous operation www. DataSheet4U. com.
  • Common data inputs and data outputs.
  • Asynchronous output enable control.
  • Available in100-pin TQFP.
  • Byte write enables.
  • Clock enable for operation hold.
  • Mu.

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Datasheet Details

Part number AS7C33512NTD18A
Manufacturer Alliance Semiconductor Corporation
File Size 484.77 KB
Description 3.3V 512K x 18 Pipelined burst Synchronous SRAM
Datasheet download datasheet AS7C33512NTD18A Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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November 2004 ® AS7C33512NTD18A 3.3V 512K × 18 Pipelined burst Synchronous SRAM with NTDTM Features • Organization: 524,288 words × 18 bits • NTD™ architecture for efficient bus operation • Fast clock speeds to 166 MHz • Fast clock to data access: 3.5/4.0 ns • Fast OE access time: 3.5/4.0 ns • Fully synchronous operation www.DataSheet4U.com • Common data inputs and data outputs • Asynchronous output enable control • Available in100-pin TQFP • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.