AS7C33512NTD18A - 3.3V 512K x 18 Pipelined burst Synchronous SRAM

Datasheet Summary

Description

The AS7C33512NTD18A family is a high performance CMOS 8 Mbit synchronous Static Random Access Memory (SRAM) organized as 524,288 words × 18 bits and incorporates a LATE LATE Write.

Features

Organization: 524,288 words × 18 bits.
NTD™ architecture for efficient bus operation.
Fast clock speeds to 166 MHz.
Fast clock to data access: 3.5/4.0 ns.
Fast OE access time: 3.5/4.0 ns.
Fully synchronous operation www. DataSheet4U. com.
Common data inputs and data outputs.
Asynchronous output enable control.
Available in100-pin TQFP.
Byte write enables.
Clock enable for operation hold.
Mu.

Alliance Semiconductor Corporation

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Datasheet Details

Part number	AS7C33512NTD18A
Manufacturer	Alliance Semiconductor Corporation
File Size	484.77 KB
Description	3.3V 512K x 18 Pipelined burst Synchronous SRAM
Datasheet	AS7C33512NTD18A Datasheet
Additional preview pages of the AS7C33512NTD18A datasheet.

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Other Datasheets by Alliance Semiconductor Corporation

AS7C33512NTD32A - (AS7C33512NTD32A / AS7C33512NTD36A) 3.3V 512K x 32/36 Pipelined SRAM
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AS7C33512NTF18A - 3.3V 512K x 18 Flowthrough Synchronous SRAM
AS7C33512NTF32A - (AS7C33512NTF32A / AS7C33512NTF36A) 3.3V 512K x 32/36 Flowthrough Synchronous SRAM
AS7C33512NTF36A - (AS7C33512NTF32A / AS7C33512NTF36A) 3.3V 512K x 32/36 Flowthrough Synchronous SRAM
AS7C33512FT18A - 3.3V 512K x 18 Flow-through synchronous SRAM
AS7C33512FT32A - (AS7C33512FT32A / AS7C33512FT36A) 3.3V 512K x 32/36 Flow-through synchronous SRAM
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Full PDF Text Transcription

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November 2004 ® AS7C33512NTD18A 3.3V 512K × 18 Pipelined burst Synchronous SRAM with NTDTM Features • Organization: 524,288 words × 18 bits • NTD™ architecture for efficient bus operation • Fast clock speeds to 166 MHz • Fast clock to data access: 3.5/4.0 ns • Fast OE access time: 3.5/4.0 ns • Fully synchronous operation www.DataSheet4U.com • Common data inputs and data outputs • Asynchronous output enable control • Available in100-pin TQFP • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.

Published: Jan 1, 2009 |