Description
The AS7C3364PFD32B and AS7C3364PFD36B are high-performance CMOS 2-Mbit synchronous Static Random Access Memory (SRAM) devices organized as 65,536 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any given technology.
Features
- Organization: 65,536 words × 32 or 36 bits.
- Fast clock speeds to 200 MHz.
- Fast clock to data access: 3.0/3.5/4.0 ns.
- Fast OE access time: 3.0/3.5/4.0 ns.
- Fully synchronous register-to-register operation.
- Double-cycle deselect.
- Asynchronous output enable control.
- Available in 100-pin TQFP package www. DataSheet4U. com.
- Linear or interleaved burst control In.