ASM3P623S00D Datasheet PDF (Zero Cycle Slip Peak EMI reduction IC) | Download Alliance Semiconductor Corporation ASM3P623S00D

ASM3P623S00D - Zero Cycle Slip Peak EMI reduction IC

This page provides the datasheet information for the ASM3P623S00D, a member of the ASM3P623S00A Zero Cycle Slip Peak EMI reduction IC family.

Description

ASM3P623S00D/E/F is a versatile, 3.3V zero-delay buffer designed to distribute high-speed clocks.

It accepts one reference input and drives out eight low-skew clocks.

It is available in a 16pin package.

Features

Input frequency range: 20MHz - 50MHz. Zero input - output propagation delay. Low-skew outputs.
Output-output skew less than 250pS. Device-device skew less than 700pS. All parts have on-chip PLLs that lock to an input clock on the CLKIN pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad, internal to the device. Multiple ASM3P623S00D/E/F devices can accept the same input clock and distribute it. In this case, the skew between the outputs.

Datasheet Details

Part number	ASM3P623S00D
Manufacturer	Alliance Semiconductor Corporation
File Size	339.76 KB
Description	Zero Cycle Slip Peak EMI reduction IC
Datasheet	ASM3P623S00D Datasheet
Additional preview pages of the ASM3P623S00D datasheet.

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Full PDF Text Transcription

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July 2005 www.DataSheet4U.com rev 1.0 ASM3P623S00A/B/C/D/E/F Zero Cycle Slip Peak EMI reduction IC General Features Input frequency range: 20MHz - 50MHz. Zero input - output propagation delay. Low-skew outputs. Output-output skew less than 250pS. Device-device skew less than 700pS. All parts have on-chip PLLs that lock to an input clock on the CLKIN pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad, internal to the device. Multiple ASM3P623S00D/E/F devices can accept the same input clock and distribute it. In this case, the skew between the outputs of the two devices is guaranteed to be less than 700pS. All outputs have less than 200pS of cycle-to-cycle jitter.

Published: Mar 3, 2009 |