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ASM5P2304A - 3.3V Zero Delay Buffer

General Description

ASM5P2304A is a versatile, 3.3V zero-delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom and other high-performance applications.

It is available in 8 pin package.

Key Features

  • Zero input - output propagation delay, adjustable by capacitive load on FBK input. Multiple configurations - Refer “ASM5P2304A Configurations Table”. Input frequency range: 15MHz to 133MHz Multiple low-skew outputs. Output-output skew less than 200pS. Device-device skew less than 500pS. Two banks of four outputs. Less than 200pS Cycle-to-Cycle jitter (-1, -1H, -2, -2H). Available in space saving, 8 pin 150-mil SOIC packages. 3.3V operation. Advanced 0.35< CMOS technology. Industrial temperature.

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Datasheet Details

Part number ASM5P2304A
Manufacturer Alliance Semiconductor Corporation
File Size 340.17 KB
Description 3.3V Zero Delay Buffer
Datasheet download datasheet ASM5P2304A Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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September 2005 rev 1.4 www.DataSheet4U.com ASM5P2304A 3.3V Zero Delay Buffer Features Zero input - output propagation delay, adjustable by capacitive load on FBK input. Multiple configurations - Refer “ASM5P2304A Configurations Table”. Input frequency range: 15MHz to 133MHz Multiple low-skew outputs. Output-output skew less than 200pS. Device-device skew less than 500pS. Two banks of four outputs. Less than 200pS Cycle-to-Cycle jitter (-1, -1H, -2, -2H). Available in space saving, 8 pin 150-mil SOIC packages. 3.3V operation. Advanced 0.35< CMOS technology. Industrial temperature available. the REF pin. The PLL feedback is required to be driven to FBK pin, and can be obtained from one of the outputs.