Datasheet4U Logo Datasheet4U.com

ASM5P2304B - 3.3V Zero Delay Buffer

General Description

ASM5P2304B is a versatile, 3.3V zero-delay buffer designed to distribute workstation, datacom, telecom and other high-performance applications.

It is available in an 8 pin package.

Key Features

  • Zero input - output propagation delay, adjustable by capacitive load on FBK input. Multiple configurations - Refer “ASM5P2304B Configurations Table”. Input frequency range: 4MHz to 20MHz Multiple low-skew outputs.
  • Output-output skew less than 200pS. Device-device skew less than 500pS. Two banks of four outputs. has an on-chip PLL, which locks to an input clock, presented on the REF pin. The PLL feedback is required to be driven t.

📥 Download Datasheet

Datasheet Details

Part number ASM5P2304B
Manufacturer Alliance Semiconductor Corporation
File Size 397.88 KB
Description 3.3V Zero Delay Buffer
Datasheet download datasheet ASM5P2304B Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
ASM5P2304A 3.3V Zero Delay Buffer ON Semiconductor
ASM5P2305A 3.3V Zero Delay Buffer ON Semiconductor
ASM5P2309A 3.3V Zero Delay Buffer ON Semiconductor
ASM51AA (ASM51AA - ASM54AA) Crystal Controlled Oscillators Connor-Winfield
ASM5206C VERY LOW-COST VOICE SYNTHESIZER Apuls Intergrated Circuits

Other Datasheets by Alliance Semiconductor Corporation

Part Number Description
ASM5P2304A 3.3V Zero Delay Buffer
ASM5P2305A (ASM5P2305A / ASM5P2309A) 3.3V Zero Delay Buffer
ASM5P2308A 3.3V Zero Delay Buffer
ASM5P2309A (ASM5P2305A / ASM5P2309A) 3.3V Zero Delay Buffer
ASM5P2309NZ Nine Output 3.3V Buffer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
September 2005 www.DataSheet4U.com rev 0.5 ASM5P2304B 3.3V Zero Delay Buffer Features ƒ ƒ ƒ ƒ Zero input - output propagation delay, adjustable by capacitive load on FBK input. Multiple configurations - Refer “ASM5P2304B Configurations Table”. Input frequency range: 4MHz to 20MHz Multiple low-skew outputs. ƒ ƒ ƒ ƒ ƒ ƒ ƒ Output-output skew less than 200pS. Device-device skew less than 500pS. Two banks of four outputs. has an on-chip PLL, which locks to an input clock, presented on the REF pin. The PLL feedback is required to be driven to FBK pin, and can be obtained from one of the outputs. The input-to-output propagation delay is guaranteed to be less than 250pS, and the output-to-output skew is guaranteed to be less than 200pS. The ASM5P2304B has two banks of two outputs each.