Datasheet4U Logo Datasheet4U.com

AS4C1G8D3LA - 8Gbit DDR3L SDRAM

Description

Clock : CK and CK are differential clock inputs.

Features

  • - Double-data-rate architecture; two data transfers per clock cycle - The high-speed data transfer is realized by the 8 bits prefetch pipe- lined architecture - Bi-directional differential data strobe (DQS and DQS) is transmitted/ received with data for capturing data at the receiver - DQS is edge-aligned with data for READs; center-aligned with data for WRITEs - Differential clock inputs (CK and CK) - DLL aligns DQ and DQS transitions with CK transitions - Commands entered on each positive CK e.

📥 Download Datasheet

Datasheet preview – AS4C1G8D3LA

Datasheet Details

Part number AS4C1G8D3LA
Manufacturer Alliance Semiconductor
File Size 2.14 MB
Description 8Gbit DDR3L SDRAM
Datasheet download datasheet AS4C1G8D3LA Datasheet
Additional preview pages of the AS4C1G8D3LA datasheet.

📁 Similar Datasheet

  • AS4C1024 - 1M x 1 DRAM (Austin Semiconductor)
  • AS4C1259 - 256K x 1 DRAM (Austin Semiconductor)
  • AS4C1259883C - 256K x 1 DRAM (Austin Semiconductor)
  • AS4C1M16S - 1M x 16 bit Synchronous DRAM (Alliance Memory)
  • AS4C1M16S-C - 1M x 16 bit Synchronous DRAM (Alliance Memory)
  • AS4C1M16S-I - 1M x 16 bit Synchronous DRAM (Alliance Memory)
  • AS4C4067 - 64K x 4 DRAM (Austin Semiconductor)
  • AS4C4256 - (Austin Semiconductor)
  • AS4C4256883C - 256K x 4 DRAM (Austin Semiconductor)
  • AS4C4M4 - 16M FPM DRAM (Austin Semiconductor)
Other Datasheets by Alliance Semiconductor

Full PDF Text Transcription

Click to expand full text
Revision History 8Gbit DDR3L SDRAM 8 BANKS X 128Mbit X 8 - Dual Die Package (DDP) 78ball FBGA Package Revision Details Rev 1.0 Preliminary datasheet AS4C1G8D3LA Date Feb. 2019 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 41 - Rev.1.0. Feb.2019 AS4C1G8D3LA Specifications - Density : 8G bits - Organization : - 128M words x 8 bits x 8 banks - Package : - 78-ball FBGA - Two 1Gbit x 4 dies stacked (DDP) - Lead-free (RoHS compliant) and Halogen-free - Power supply : VDD, VDDQ = 1.35V (1.283V to 1.45V) - -Backward compatible to VDD, VDDQ = 1.5V ± 0.
Published: |