AS4C1G8D3LA Description
2019 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 620-9211 Alliance Memory Inc.
AS4C1G8D3LA Key Features
- Double-data-rate architecture; two data transfers per clock cycle
- The high-speed data transfer is realized by the 8 bits prefetch pipe
- Bi-directional differential data strobe (DQS and DQS) is transmitted/
- DQS is edge-aligned with data for READs; center-aligned with data
- Differential clock inputs (CK and CK)
- DLL aligns DQ and DQS transitions with CK transitions
- mands entered on each positive CK edge; data and data mask
- Data mask (DM) for write data
- Posted CAS by programmable additive latency for better mand
- On-Die Termination (ODT) for better signal quality