Description
Address inputs Row address strobe Input/output Output enable Write enable Column address strobe, upper byte Column address strobe, lower byte
Symbol tRAC tAA tCAC tOEA tRC tHPC ICC1 ICC5
-45 45 23 10 12 75 20 155 2.0
-50 50 25 12 13 80 20 145 2.0
-60 60 30 15 15 100
Unit ns ns ns ns ns mA mA
Features
- hyper page mode operation where read and write operations within a single row (or page) can be executed at very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling edge of RAS and xCAS inputs, respectively. Also, RAS is used to make the column address latch transparent, enabling.
AS4C1M16E5 Datasheet
