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AS4C1M16E5 Datasheet 5v 1m X 16 CMOS Dram

Manufacturer: Alliance Semiconductor

Overview: $XJXVW  Š $6&0( 9 0î &026 '5$0 ('2 )HDWXUHV • Organization: 1,048,576 words × 16 bits • High speed - 45/50/60 ns RAS access time - 20/20/25 ns hyper page cycle time - 10/12/15 ns CAS access time • 1024 refresh cycles, 16 ms refresh interval - RAS-only or CAS-before-RAS refresh Read-modify-write • TTL-patible, three-state DQ • JEDEC standard package and pinout - 400 mil, 42-pin SOJ - 400 mil, 44/50-pin TSOP 2 • Low power consumption - Active: 740 mW max (AS4C1M16E5-60) - Standby: 5.5 mW max, CMOS DQ • 5V power supply • Industrial and mercial temperature available • Extended data out 3LQ DUUDQJHPHQW 62Vcc DQ1 DQ2 DQ3 '4 Vcc DQ5 DQ6 DQ7 DQ8 NC NC WE RAS NC NC A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 V66 DQ16 DQ15 DQ14 DQ13 V66 DQ12 DQ11 DQ10 DQ9 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 V66 V&& DQ1 DQ2 DQ DQ4 V&& DQ5 DQ6 DQ7 DQ8 NC 1 2 3 4 5 6 7 8 9 10 11 3LQ GHVLJQDWLRQ 7623  50 49 48 47 46 45 44 43 42 41 40 V66 DQ16 DQ15 DQ14 DQ13 V66 DQ12 DQ11 DQ10 DQ9 NC Pin(s) A0 to A9 RAS 6HOHFWLRQ JXLGH Maximum RAS access time Maximum column address access time Maximum CAS access time Maximum output enable (OE) access time Minimum read or write cycle time Minimum hyper page mode cycle time Maximum operating current Maximum CMOS standby current w w w NC NC WE RAS NC NC A0 A1 A2 A3 V&& .D 15 16 17 18 19 20 21 22 23 24 25 t a 36 35 34 33 32 31 30 29 28 27 26 S a NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 V66 e h OE WE UCAS LCAS VCC VSS DQ1 to DQ16 t e U 4 Power Ground .

General Description

Address inputs Row address strobe Input/output Output enable Write enable Column address strobe, upper byte Column address strobe, lower byte Symbol tRAC tAA tCAC tOEA tRC tHPC ICC1 ICC5 -45 45 23 10 12 75 20 155 2.0 -50 50 25 12 13 80 20 145 2.0 -60 60 30 15 15 100 Unit ns ns ns ns ns mA mA  Y $OOLDQFH 6HPLFRQGXFWRU w w w .D a at 135 2.0 Sh 25 t

Key Features

  • hyper page mode operation where read and write operations within a single row (or page) can be executed at very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling edge of RAS and xCAS inputs, respectively. Also, RAS is used to make the column address latch transparent, enabling.

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