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AS4C512M16D3LA - 8Gbit DDR3L SDRAM

Description

Clock : CK and CK are differential clock inputs.

Features

  • - Double-data-rate architecture; two data transfers per clock cycle - The high-speed data transfer is realized by the 8 bits prefetch pipe- lined architecture - Bi-directional differential data strobe (DQS and DQS) is transmitted/ received with data for capturing data at the receiver - DQS is edge-aligned with data for READs; center-aligned with data for WRITEs - Differential clock inputs (CK and CK) - DLL aligns DQ and DQS transitions with CK transitions - Commands entered on each positive CK e.

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Datasheet preview – AS4C512M16D3LA

Datasheet Details

Part number AS4C512M16D3LA
Manufacturer Alliance Semiconductor
File Size 1.92 MB
Description 8Gbit DDR3L SDRAM
Datasheet download datasheet AS4C512M16D3LA Datasheet
Additional preview pages of the AS4C512M16D3LA datasheet.

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Full PDF Text Transcription

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Revision History 8Gbit DDR3L SDRAM 8 BANKS X 64Mbit X 16 - Dual Die Package (DDP) 96ball FBGA Package Revision Details Rev 1.0 Preliminary datasheet AS4C512M16D3LA Date Feb. 2019 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 41 - Rev.1.0 Feb.2019 AS4C512M16D3LA Specifications - Density : 8G bits - Organization : - 64M words x 16 bits x 8 banks - Package : - 96-ball FBGA - Two 512Mbit x 8 dies stacked (DDP) - Lead-free (RoHS compliant) and Halogen-free - Power supply : VDD, VDDQ = 1.35V (1.283V to 1.45V) - -Backward compatible to VDD, VDDQ =1.5V ± 0.
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