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January 2001 Advance Information
AS7C256 AS7C3256
®
5V/3.3V 32K X 8 CMOS SRAM (Common I/O)
Features
• AS7C256 (5V version) • AS7C3256 (3.3V version) • Industrial and commercial temperature • Organization: 262,144 words × 16 bits • High speed
- 12/15/20 ns address access time - 5/6/7/9 ns output enable access time • Very low power consumption: ACTIVE - 660mW (AS7C256) / max @ 12 ns - 216mW (AS7C3256) / max @ 12 ns • Very low power consumption: STANDBY - 22 mW (AS7C256) / max CMOS I/O
Logic block diagram
- 7.2 mW (AS7C3256) / max CMOS I/O • 2.0V data retention • Easy memory expansion with CE and OE inputs • TTL-compatible, three-state I/O • 28-pin JEDEC standard packages
- 300 mil PDIP - 300 mil SOJ - 8 × 13.