AS7C33256NTD18A Overview
The AS7C33256NTD16A/18A family is a high performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) organized as 262,144 words × 16 or 18 bits and incorporates a LATE LATE Write. This variation of the 4Mb sychronous SRAM uses the No Turnaround Delay (NTD) architecture, featuring an enhanced Write operation that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write...
AS7C33256NTD18A Key Features
- Organization: 262,144 words × 16 or 18 bits
- NTD™1 architecture for efficient bus operation
- Fast clock speeds to 166 MHz in LVTTL/LVCMOS
- Fast clock to data access: 3.5/4.0/5.0 ns
- Fast OE access time: 3.5/4.0/5.0 ns
- Fully synchronous operation
- Flow-through or pipelined mode
- Asynchronous output enable control
- Economical 100-pin TQFP package
- Byte write enables
