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AS7C33256NTD18A - 3.3V 256K X 16/18 SRAM

Download the AS7C33256NTD18A datasheet PDF. This datasheet also covers the AS7C33256NTD16A variant, as both devices belong to the same 3.3v 256k x 16/18 sram family and are provided as variant models within a single manufacturer datasheet.

General Description

The AS7C33256NTD16A/18A family is a high performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) organized as 262,144 words × 16 or 18 bits and incorporates a LATE LATE Write.

Key Features

  • Organization: 262,144 words × 16 or 18 bits.
  • NTD™1 architecture for efficient bus operation.
  • Fast clock speeds to 166 MHz in LVTTL/LVCMOS.
  • Fast clock to data access: 3.5/4.0/5.0 ns.
  • Fast OE access time: 3.5/4.0/5.0 ns.
  • Fully synchronous operation.
  • Flow-through or pipelined mode.
  • Asynchronous output enable control 1 NTD is a trademark of Alliance Semiconductor Corporation.
  • Economical 100-pin TQFP package.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (AS7C33256NTD16A-AllianceSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number AS7C33256NTD18A
Manufacturer Alliance Semiconductor
File Size 162.97 KB
Description 3.3V 256K X 16/18 SRAM
Datasheet download datasheet AS7C33256NTD18A Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
December 2002 AS7C33256NTD16A AS7C33256NTD18A ® 9 .î 65$0 ZLWK 17'TM Features • Organization: 262,144 words × 16 or 18 bits • NTD™1 architecture for efficient bus operation • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/4.0/5.0 ns • Fast OE access time: 3.5/4.0/5.0 ns • Fully synchronous operation • Flow-through or pipelined mode • Asynchronous output enable control 1 NTD is a trademark of Alliance Semiconductor Corporation. • Economical 100-pin TQFP package • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.