Datasheet Details
| Part number | AS7C33256NTD18B |
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| Manufacturer | Alliance Semiconductor Corporation |
| File Size | 486.52 KB |
| Description | 3.3V 256K x 8 Pipelined SRAM |
| Datasheet |
 AS7C33256NTD18B Datasheet
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General Description
The AS7C33256NTD18B family is a high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM) organized as 262,144 words × 18 bits and incorporates a LATE LATE Write.
Key Features
- Organization: 262,144 words × 18 bits.
- NTD™ architecture for efficient bus operation.
- Fast clock speeds to 200 MHz.
- Fast clock to data access: 3.0/3.5/4.0 ns.
- Fast OE access time: 3.0/3.5/4.0 ns.
- Fully synchronous operation.
- Asynchronous output enable control.
- Available in 100-pin TQFP package www. DataSheet4U. com.
- Byte write enables.
- Clock enable for operation hold Logic block diagram A[17:0] 18 D.
