The AS7C33256NTD18B family is a high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM) organized as 262,144 words × 18 bits and incorporates a LATE LATE Write.
Features
Organization: 262,144 words × 18 bits.
NTD™ architecture for efficient bus operation.
Fast clock speeds to 200 MHz.
Fast clock to data access: 3.0/3.5/4.0 ns.
Fast OE access time: 3.0/3.5/4.0 ns.
Fully synchronous operation.
Asynchronous output enable control.
Available in 100-pin TQFP package www. DataSheet4U. com.
Byte write enables.
Clock enable for operation hold Logic block diagram
A[17:0] 18
D.
February 2005
®
AS7C33256NTD18B
3.3V 256K×18 Pipelined SRAM with NTDTM
Features • Organization: 262,144 words × 18 bits • NTD™ architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous operation • Asynchronous output enable control • Available in 100-pin TQFP package www.DataSheet4U.com • Byte write enables • Clock enable for operation hold Logic block diagram
A[17:0] 18
D
• Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.
AS7C33256NTD18B Datasheet
