EPM7000B Overview
MAX 7000B ® Programmable Logic Device Data Sheet September 2003, ver.
EPM7000B Key Features
- Pin-patible with the popular 5.0-V MAX 7000S and 3.3-V MAX 7000A device families
- High-density PLDs ranging from 600 to 10,000 usable gates
- 3.5-ns pin-to-pin logic delays with counter frequencies in excess of 303.0 MHz Advanced 2.5-V in-system programmability
- Programs through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capabi
- Enhanced ISP algorithm for faster programming
- ISP_Done bit to ensure plete programming
- Pull-up resistor on I/O pins during in-system programming
- ISP circuitry pliant with IEEE Std. 1532
- MultiVoltTM I/O interface enabling device core to run at 2.5 V, while I/O pins are patible with 3.3-V, 2.5-V, and 1.8-V
- Programmable power-saving mode for 50% or greater power reduction in each macrocell