FEATURES
PLL generated or direct master clock Low EMI design 112 dB DAC/107 dB ADC dynamic range and SNR −94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24-bits and 8 kHz to 192 kHz sample rates Differential ADC input Differential DAC output Log volume control with autoramp function SPI® controllable for flexibility Software controllable clickless mute Software power-down Right-justified, left-justified, I2S, and TDM modes Master and slave modes up to 16-channel in/out 64-lead LQFP package GENERAL DESCRIPTION
patented multibit sigma-delta (Σ-Δ) architecture. An SPI port is included, allowing a microcontroller to adjust volume and many other parameters. The AD1939 is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the master clock from the LR clock or from an external crystal, the AD1939 eliminates the need for a separate high frequency master clock and can also be used with a suppressed bit clock.
Analog Devices
