Datasheet4U Logo Datasheet4U.com

AD4129-8 - 16-Bit Sigma-Delta ADC

General Description

Companion Products5 Specifications 6 ADC and AFE Specifications6 Analog Input Specifications 7 Reference Specifications7 Sensor Biasing Specifications 8 Diagnostics Specifications9 Rejection Specifications 9 Logic Input and Output Specifications 11 Power Specifications 11 Timing Specifications 12 A

Key Features

  • Ultra-low current consumption (typical).
  • 32 µA: continuous conversion mode (gain = 128).
  • 5 µA: duty cycling mode (ratio = 1/16).
  • 0.5 µA: standby mode.
  • 0.1 µA: power-down mode.
  • Built-in features for system level power savings.
  • Current saving duty cycle ratio: 1/4 or 1/16.
  • Smart sequencer and per channel configuration minimizes host processor load.
  • Deep embedded FIFO minimizes host processor load (depth of 256 samples).
  • Autonomous FIFO interrupt f.

📥 Download Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Data Sheet AD4129-8 32 μA, Ultra-Low Power, 16-Bit Sigma-Delta ADC with Integrated PGA and FIFO FEATURES ► Ultra-low current consumption (typical) ► 32 µA: continuous conversion mode (gain = 128) ► 5 µA: duty cycling mode (ratio = 1/16) ► 0.5 µA: standby mode ► 0.1 µA: power-down mode ► Built-in features for system level power savings ► Current saving duty cycle ratio: 1/4 or 1/16 ► Smart sequencer and per channel configuration minimizes host processor load ► Deep embedded FIFO minimizes host processor load (depth of 256 samples) ► Autonomous FIFO interrupt functionality, threshold detection ► Single supply as low as 1.71 V increasing battery length ► RMS noise: 25 nV rms at 1.17 SPS (gain = 128) = 48 nV/√Hz ► Up to 16 noise free bits (gain = 1) ► Output data rate: 1.17 SPS to 2.