AD4129-4 Datasheet | Analog Devices

Data Sheet AD4129-4 32 μA, Ultra-Low Power, 16-Bit Sigma-Delta ADC with Integrated PGA and FIFO Features - Ultra-low current consumption (typical) - 32 µA: continuous conversion mode (gain = 128) - 5 µA: duty cycling mode (ratio = 1/16) - 0.5 µA: standby mode - 0.1 µA: power-down mode - Built-in Features for system level power savings - Current saving duty cycle ratio: 1/4 or 1/16 - Smart sequencer and per channel configuration minimizes host processor load - Deep embedded FIFO minimizes host processor load (depth of 256 samples) - Autonomous FIFO interrupt functionality, threshold detection - Single supply as low as 1.71 V increasing battery length - RMS noise: 25 nV rms at 1.17 SPS...