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AD5684 - Quad nanoDAC

This page provides the datasheet information for the AD5684, a member of the AD5686 Quad nanoDAC family.

Datasheet Summary

Description

The AD5686/AD5684, members of the nanoDAC+™ family, are low power, quad, 16-/12-bit buffered voltage output DACs.

The devices include a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2).

Features

  • High relative accuracy (INL): ±2 LSB maximum @ 16 bits.
  • Tiny package: 3 mm × 3 mm, 16-lead LFCSP.
  • Total unadjusted error (TUE): ±0.1% of FSR maximum.
  • Offset error: ±1.5 mV maximum.
  • Gain error: ±0.1% of FSR maximum.
  • High drive capability: 20 mA, 0.5 V from supply rails.
  • User selectable gain of 1 or 2 (GAIN pin).
  • Reset to zero scale or midscale (RSTSEL pin).
  • 1.8 V logic compatibility.
  • 50 MHz SPI with readback or daisy chain.
  • Low glitch: 0.5 n.

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Datasheet preview – AD5684

Datasheet Details

Part number AD5684
Manufacturer Analog Devices
File Size 2.21 MB
Description Quad nanoDAC
Datasheet download datasheet AD5684 Datasheet
Additional preview pages of the AD5684 datasheet.

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Full PDF Text Transcription

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Data Sheet AD5686/AD5684 Quad, 16-/12-Bit nanoDAC+ with SPI Interface FEATURES ► High relative accuracy (INL): ±2 LSB maximum @ 16 bits ► Tiny package: 3 mm × 3 mm, 16-lead LFCSP ► Total unadjusted error (TUE): ±0.1% of FSR maximum ► Offset error: ±1.5 mV maximum ► Gain error: ±0.1% of FSR maximum ► High drive capability: 20 mA, 0.5 V from supply rails ► User selectable gain of 1 or 2 (GAIN pin) ► Reset to zero scale or midscale (RSTSEL pin) ► 1.8 V logic compatibility ► 50 MHz SPI with readback or daisy chain ► Low glitch: 0.5 nV-sec ► Low power: 1.8 mW at 3 V ► 2.7 V to 5.
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