AD5684 Datasheet | Analog Devices

Data Sheet AD5686/AD5684 Quad, 16-/12-Bit nano DAC+ with SPI Interface Features - High relative accuracy (INL): ±2 LSB maximum @ 16 bits - Tiny package: 3 mm × 3 mm, 16-lead LFCSP - Total unadjusted error (TUE): ±0.1% of FSR maximum - Offset error: ±1.5 m V maximum - Gain error: ±0.1% of FSR maximum - High drive capability: 20 m A, 0.5 V from supply rails - User selectable gain of 1 or 2 (GAIN pin) - Reset to zero scale or midscale (RSTSEL pin) - 1.8 V logic patibility - 50 MHz SPI with readback or daisy chain - Low glitch: 0.5 n V-sec - Low power: 1.8 m W at 3 V - 2.7 V to 5.5 V power supply - - 40°C to +105°C temperature range APPLICATIONS - Digital gain and offset adjustment - Programmable attenuators - Process control (PLC I/O cards) - Industrial automation - Data acquisition systems GENERAL DESCRIPTION The AD5686/AD5684, members of the nano DAC+™ family, are low power, quad, 16-/12-bit buffered voltage output DACs. The devices include a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). All devices operate from a single 2.7 V to 5.5 V supply, are guaranteed monotonic by design, and exhibit less than 0.1% FSR gain error and 1.5 m V offset error performance. The devices are available in a 3 mm × 3 mm LFCSP and a TSSOP package. The AD5686/AD5684 also incorporate a power-on reset circuit and a RSTSEL pin that ensures that the DAC outputs power up to zero scale or midscale and remain at that level until a valid write takes place. Each part contains a per-channel power-down feature that reduces the current consumption of the device to 4 µA at 3 V while in power-down mode. The AD5686/AD5684 employ a versatile SPI interface that operates at clock rates up to 50 MHz, and all devices contain a VLOGIC pin intended for 1.8 V/3 V/5 V logic. FUNCTIONAL BLOCK DIAGRAM Figure 1. Table 1. Quad nano DAC+...