AD6121 Datasheet | Analog Devices

FEATURES Fully pliant with IS98A and PCS Specifications CDMA, W-CDMA, AMPS, and TACS Operation Linear IF Amplifier 5.9 d B Noise Figure - 47.5 d B to +47 d B Linear-in-d B Gain Control Quadrature Demodulator Demodulates IFs from 50 MHz to 350 MHz Integral Low Dropout Regulator 200 m V Voltage Drop Accepts 2.9 V to 4.2 V Input from Battery Low Power 10 m A at Midgain <1 ␮ A Sleep Mode Operation panion Transmitter IF Chip Available (AD6122) APPLICATIONS CDMA, W-CDMA, AMPS, and TACS Operation QPSK Receivers CDMA 3 V Receiver IF Subsystem with Integrated Voltage Regulator AD6121 GENERAL DESCRIPTION The AD6121 is a low power receiver IF subsystem specifically designed for CDMA applications. It consists of high dynamic range IF amplifiers with voltage controlled gain, a divide-by-two quadrature generator, an I and Q demodulator, and a powerdown control input. An integral low dropout regulator allows operation from battery voltages from 2.9 V to 4.2 V. The gain control input accepts an external gain control voltage input from a DAC. It provides 94.5 d B of gain control with a nominal 52.5 d B/V scale factor when using an internal voltage reference. The gain control interface reference input can be connected to either the internal reference or an external reference. The I and Q demodulator provides differential quadrature baseband outputs to interface with CDMA baseband converters. A divide-by-two quadrature generator followed by dual polyphase filters ensures maximum ± 2.5° quadrature accuracy. The AD6121 IF Subsystem is fabricated using a 25 GHz f t Bi CMOS silicon process and is packaged in a 28-lead SSOP and a 32-leadless LPCC chip scale package (5 mm × 5 mm). FUNCTIONAL BLOCK DIAGRAM ROOFING FILTER IF OUTPUT DEMODULATOR INPUT IOUT CDMA INPUT IF AMPLIFIERS IOUT I 2 Q LOCAL OSCILLATOR INPUT QOUT QOUT QUADRATURE DEMODULATOR FM INPUT INPUT STAGE VREG PTAT TEMPERATURE PENSATION GAIN CONTROL SCALE FACTOR LOW DROPOUT REGULATOR VPOS CDMA/FM SELECT GAIN CONTROL...