AD6620 Description
REAL, DUAL REAL, OR PLEX INPUTS 65 MSPS Digital Receive Signal Processor AD6620 FUNCTIONAL BLOCK DIAGRAM I CIC FILTERS I FIR FILTER I OUTPUT FORMAT SERIAL OR PARALLEL OUTPUTS Q COS SIN Q Q PLEX NCO EXTERNAL SYNC CIRCUITRY JTAG PORT P OR SERIAL CONTROL both narrowband and wideband carriers to be extracted. The RAM-based architecture allows easy reconfiguration for multimode applications. The decimating filters...