FEATURES
80 MSPS Wide Band Inputs (14 Linear Bits Plus 3 RSSI) Dual High Speed Data Input Ports Four Independent Digital Receivers in Single Package Digital Resampling for Noninteger Decimation Rates Programmable Decimating FIR Filters Programmable Attenuator Control for Clip Prevention and External Gain Ranging via Level Indicator Flexible Control for Multicarrier and Phased Array 3.3 V I/O, 2.5 V CMOS Core User-Configurable Built-In Self-Test (BIST) Capability JTAG Boundary Scan APPLICATIONS
Multicarrier, Multimode Digital Receivers GSM, IS136, EDGE, PHS, IS95 Micro and Pico Cell Systems Wireless Local Loop Smart Antenna Systems Software Radios In-Building Wireless Telephony PRODUCT DESCRIPTION
Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) AD6624 High dynamic range decimation filters offer a wide range of decimation rates. The RAM-based architecture allows easy reconfiguration for multimode applications. The decimating filters remove unwanted signals and noise from the channel of interest.
Analog Devices
