Datasheet4U Logo Datasheet4U.com

AD7175-8 - SigmaDelta ADC

Datasheet Summary

Description

Fast and flexible output rate: 5 SPS to 250 kSPS Channel scan data rate of 50 kSPS/channel (20 µs settling) Performance specifications 17.2 noise free bits at 250 kSPS 20.2 noise free bits at 2.5 kSPS 24 noise free bits at 20 SPS INL: ±1 ppm of FSR 85 dB filter rejection of 50 Hz and 60 Hz with 50

📥 Download Datasheet

Datasheet preview – AD7175-8

Datasheet Details

Part number AD7175-8
Manufacturer Analog Devices
File Size 1.06 MB
Description SigmaDelta ADC
Datasheet download datasheet AD7175-8 Datasheet
Additional preview pages of the AD7175-8 datasheet.

📁 Similar Datasheet

  • AD7216N2L - AC-DC / External Freestanding Adapter (Emerson)
  • AD7315 - Low Quiescent Current Low Dropout CMOS Voltage Regulator (Advanced Corporation Limited)
  • AD7318 - Low Quiescent Current Low Dropout CMOS Voltage Regulator (Advanced Corporation Limited)
  • AD7325 - Low Quiescent Current Low Dropout CMOS Voltage Regulator (Advanced Corporation Limited)
  • AD7328 - Low Quiescent Current Low Dropout CMOS Voltage Regulator (Advanced Corporation Limited)
  • AD7330 - Low Quiescent Current Low Dropout CMOS Voltage Regulator (Advanced Corporation Limited)
  • AD7333 - Low Quiescent Current Low Dropout CMOS Voltage Regulator (Advanced Corporation Limited)
  • AD7336 - Low Quiescent Current Low Dropout CMOS Voltage Regulator (Advanced Corporation Limited)
  • AD7344 - Low Quiescent Current Low Dropout CMOS Voltage Regulator (Advanced Corporation Limited)
  • AD7350 - Low Quiescent Current Low Dropout CMOS Voltage Regulator (Advanced Corporation Limited)
Other Datasheets by Analog Devices

Full PDF Text Transcription

Click to expand full text
Data Sheet 24-Bit, 8-/16-Channel, 250 kSPS, SigmaDelta ADC with True Rail-to-Rail Buffers AD7175-8 FEATURES GENERAL DESCRIPTION Fast and flexible output rate: 5 SPS to 250 kSPS Channel scan data rate of 50 kSPS/channel (20 µs settling) Performance specifications 17.2 noise free bits at 250 kSPS 20.2 noise free bits at 2.5 kSPS 24 noise free bits at 20 SPS INL: ±1 ppm of FSR 85 dB filter rejection of 50 Hz and 60 Hz with 50 ms settling User configurable input channels 8 fully differential channels or 16 single-ended channels Crosspoint multiplexer On-chip 2.5 V reference (±2 ppm/°C drift) True rail-to-rail analog and reference input buffers Internal or external clock Power supply: AVDD1 − AVSS = 5 V, AVDD2 = IOVDD = 2 V to 5 V (nominal) Split supply with AVDD1/AVSS at ±2.
Published: |