AD9281 Datasheet | Analog Devices

FEATURES plete Dual Matching ADC Low Power Dissipation: 225 m W (+3 V Supply) Single Supply: 2.7 V to 5.5 V Differential Nonlinearity Error: 0.1 LSB On-Chip Analog Input Buffers On-Chip Reference Signal-to-Noise Ratio: 49.2 d B Over Seven Effective Bits Spurious-Free Dynamic Range: - 65 d B No Missing Codes Guaranteed 28-Lead SSOP Dual Channel 8-Bit Resolution CMOS ADC IINA IINB IREFB IREFT QREFB QREFT VREF REFSENSE QINB QINA FUNCTIONAL BLOCK DIAGRAM AVDD AVSS CLOCK DVDD DVSS "I" ADC I REGISTER REFERENCE BUFFER ASYNCHRONOUS MULTIPLEXER 1V THREESTATE OUTPUT BUFFER "Q" ADC Q REGISTER SLEEP SELECT DATA 8 BITS CHIP SELECT PRODUCT DESCRIPTION The AD9281 is a plete dual channel, 28 MSPS, 8-bit CMOS ADC. The AD9281 is optimized specifically for applications where close matching between two ADCs is required (e.g., I/Q channels in munications applications). The 28 MHz sampling rate and wide input bandwidth will cover both narrowband and spread-spectrum channels. The AD9281 integrates two 8-bit, 28 MSPS ADCs, two input buffer amplifiers, an internal voltage reference and multiplexed digital output buffers. Each ADC incorporates a simultaneous sampling sample-andhold amplifier at its input. The analog inputs are buffered; no external input buffer op amp will be required in most applications. The ADCs are implemented using a multistage pipeline architecture that offers accurate performance and guarantees no missing codes. The outputs of the ADCs are ported to a multiplexed digital output buffer. The AD9281 is manufactured on an advanced low cost CMOS process, operates from a single supply from 2.7 V to 5.5 V, and consumes 225 m W of power (on 3 V supply). The AD9281 input structure accepts either single-ended or differential signals, providing excellent dynamic performance up to and beyond 14 MHz Nyquist input frequencies. PRODUCT HIGHLIGHTS 1. Dual 8-Bit, 28 MSPS ADC A pair of high performance 28 MSPS ADCs that are optimized for spurious free dynamic...