AD9522-5 Datasheet | Analog Devices

Data Sheet Features Low phase noise, phase-locked loop (PLL) Supports external 3.3 V/5 V voltage controlled oscillator (VCO)/VCXO to 2.4 GHz 1 differential or 2 single-ended reference inputs Accepts CMOS, LVPECL, or LVDS references to 250 MHz Accepts 16.62 MHz to 33.3 MHz crystal for reference input Optional reference clock doubler Reference monitoring capability Revertive automatic and manual reference switchover/ holdover modes Glitch-free switchover between references Automatic recovery from holdover Digital or analog lock detect, selectable Optional zero delay operation Twelve 800 MHz LVDS outputs divided into 4 groups Each group of 3 has a 1-to-32 divider with phase delay Additive...