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AD9550 - Integer-N Clock Translator

General Description

The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications.

The device employs an integer-N PLL to accommodate the applicable frequency translation requirements.

Key Features

  • Converts preset standard input frequencies to standard output frequencies Input frequencies from 8 kHz to 200 MHz Output frequencies up to 810 MHz LVPECL and LVDS (200 MHz CMOS) Preset pin-programmable frequency translation ratios On-chip VCO Single-ended CMOS reference input Two output clocks (independently programmable as LVDS, LVPECL, or CMOS) Single supply (3.3 V) Very low power:.

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Other Datasheets by Analog Devices

Part Number Description
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AD9501 Digitally Programmable Delay Generator

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Integer-N Clock Translator for Wireline Communications AD9550 FEATURES Converts preset standard input frequencies to standard output frequencies Input frequencies from 8 kHz to 200 MHz Output frequencies up to 810 MHz LVPECL and LVDS (200 MHz CMOS) Preset pin-programmable frequency translation ratios On-chip VCO Single-ended CMOS reference input Two output clocks (independently programmable as LVDS, LVPECL, or CMOS) Single supply (3.3 V) Very low power: <450 mW (under most conditions) Small package size (5 mm × 5 mm) Exceeds Telcordia GR-253-CORE jitter generation, transfer and tolerance specifications BASIC BLOCK DIAGRAM REF PLL OUTPUT CIRCUITRY OUT2 OUT1 PIN DECODER 09057-001 AD9550 Figure 1.