Datasheet4U Logo Datasheet4U.com

AD9550 - Integer-N Clock Translator

Description

The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications.

The device employs an integer-N PLL to accommodate the applicable frequency translation requirements.

Features

  • Converts preset standard input frequencies to standard output frequencies Input frequencies from 8 kHz to 200 MHz Output frequencies up to 810 MHz LVPECL and LVDS (200 MHz CMOS) Preset pin-programmable frequency translation ratios On-chip VCO Single-ended CMOS reference input Two output clocks (independently programmable as LVDS, LVPECL, or CMOS) Single supply (3.3 V) Very low power:.

📥 Download Datasheet

Datasheet preview – AD9550

Datasheet Details

Part number AD9550
Manufacturer Analog Devices
File Size 741.57 KB
Description Integer-N Clock Translator
Datasheet download datasheet AD9550 Datasheet
Additional preview pages of the AD9550 datasheet.

📁 Similar Datasheet

  • AD9256 - DIGITAL AMPLIFIER POWER STAGE (Elite Semiconductor)
  • AD9256H - DIGITAL AMPLIFIER POWER STAGE (Elite Semiconductor)
  • AD92580 - DIGITAL AMPLIFIER POWER STAGE (Elite Semiconductor)
  • AD92580C - DIGITAL AMPLIFIER POWER STAGE (Elite Semiconductor)
  • AD9700 - Video Dispaly D/A Converter (ETC)
Other Datasheets by Analog Devices
  • AD9551 - Multiservice Clock Generator
  • AD9552 - Oscillator Frequency Up Converter
  • AD9553 - Flexible Clock Translator
  • AD9554 - Multiservice Line Card Adaptive Clock Translator
  • AD9554-1 - Multiservice Line Card Adaptive Clock Translator
  • AD9557 - Dual Input Multiservice Line Card Adaptive Clock Translator
  • AD9558 - Quad Input Multiservice Line Card Adaptive Clock Translator
  • AD9559 - Multiservice Line Card Adaptive Clock Translator

Full PDF Text Transcription

Click to expand full text
Integer-N Clock Translator for Wireline Communications AD9550 FEATURES Converts preset standard input frequencies to standard output frequencies Input frequencies from 8 kHz to 200 MHz Output frequencies up to 810 MHz LVPECL and LVDS (200 MHz CMOS) Preset pin-programmable frequency translation ratios On-chip VCO Single-ended CMOS reference input Two output clocks (independently programmable as LVDS, LVPECL, or CMOS) Single supply (3.3 V) Very low power: <450 mW (under most conditions) Small package size (5 mm × 5 mm) Exceeds Telcordia GR-253-CORE jitter generation, transfer and tolerance specifications BASIC BLOCK DIAGRAM REF PLL OUTPUT CIRCUITRY OUT2 OUT1 PIN DECODER 09057-001 AD9550 Figure 1.
Published: |