FEATURES
1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR 74.3 dBFS at 9.7 MHz input 71.5 dBFS at 200 MHz input SFDR 93 dBc at 9.7 MHz input 80 dBc at 200 MHz input Low power 45 mW at 20 MSPS 87 mW at 80 MSPS Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = ±0.35 LSB Serial port control options Offset binary, gray code, or twos complement data format Integer 1, 2, or 4 input clock divider Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out (DCO) with programmable clock and data alignment APPLICATIONS
Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems Battery-powered instruments Handheld scope meters Portable medical imaging Ultrasound Radar/LIDAR RBIAS VCM VIN+ VIN– VREF SENSE FUNCTIONAL BLOCK DIAGRAM AVDD GND SDIO SCLK CSB DRVDD SPI PROGRAMMING DATA ADC CORE CMOS OUTPUT BUFFER OR D13 (MSB) D0 (LSB) DCO REF SELECT DIVIDE BY 1, 2, 4 AD9649 MODE CONTROLS 08539-001 CLK+ CLK– PDWN DFS MODE Figure 1.