ADAU1977 Datasheet | Analog Devices

FEATURES Programmable microphone bias (5 V to 9 V) with diagnostics Four 10 V rms capable direct-coupled differential inputs On-chip PLL for master clock Low EMI design 109 d B ADC dynamic range - 95 d B THD + N Selectable digital high-pass filter 24-bit ADC with 8 k Hz to 192 k Hz sample rates Digital volume control with autoramp function I2C/SPI control Software-controllable clickless mute Software power-down Right justified, left justified, I2S justified, and TDM modes Master and slave operation modes 40-lead LFCSP package Qualified for automotive applications APPLICATIONS Automotive audio systems Active noise cancellation system Quad ADC with Diagnostics GENERAL DESCRIPTION The ADAU1977 incorporates four high performance analogto-digital converters (ADCs) with direct-coupled inputs capable of 10 V rms. The ADC uses multibit sigma-delta (Σ-Δ) architecture with continuous time front end for low EMI. The ADCs can be connected to the electret microphone (ECM) directly and provide the bias for powering the microphone. Built-in diagnostic circuitry detects faults on input lines and includes prehensive diagnostics for faults on microphone inputs. The faults reported are short to battery, short to microphone bias, short to ground, short between positive and negative input pins, and open input terminals. In addition, each diagnostic fault is available as an IRQ flag for ease in system design. An I2C/SPI control port is also included. The ADAU1977 uses only a single 3.3 V supply. The part internally generates the microphone bias voltage. The microphone bias is programmable in a few steps from 5 V to 9 V. The low power architecture reduces the power consumption. An on-chip PLL can derive the master clock from an external clock input or frame clock (sample rate clock). When fed with a frame clock, the PLL eliminates the need for a separate high frequency master clock in the system. The ADAU1977 is available in a 40-lead LFCSP package. Rev. D Document Feedback Inform...