ADAU1979 Datasheet | Analog Devices

FEATURES Four 4.5 V rms (typical) differential inputs On-chip phase-locked loop (PLL) for master clock Low electromagnetic interference (EMI) design 109 d B (typical) analog-to-digital converter (ADC) dynamic range Total harmonic distortion + noise (THD + N): - 95 d B (typical) Selectable digital high-pass filter 24-bit stereo ADC with 8 k Hz to 192 k Hz sample rates Digital volume control with autoramp function I2C/SPI controllable for flexibility Software-controllable clickless mute Software power-down Right justified, left justified, I2S, and TDM modes Master and slave operation modes 40-lead LFCSP Qualified for automotive applications APPLICATIONS Automotive audio systems Active noise cancellation systems GENERAL DESCRIPTION The ADAU1979 incorporates four high performance, analog-to-digital converters (ADCs) with 4.5 V rms capable ac-coupled inputs. The ADCs use a multibit sigma-delta (ΣΔ) architecture with continuous time front end for low EMI. An I2C/serial peripheral interface (SPI) control port is included that allows a microcontroller to adjust volume and many other parameters. The ADAU1979 uses only a single 3.3 V supply. The device internally generates the required digital DVDD supply. The low power architecture reduces the power consumption. The on-chip PLL can derive the master clock from an external clock input or frame clock (sample rate clock). When fed with the frame clock, it eliminates the need for a separate high frequency master clock in the system. The ADAU1979 is available in a 40-lead LFCSP. Note that throughout this data sheet, multifunction pins, such as SCL/CCLK, are referred to either by the entire pin name or by a single function of the pin, for example, CCLK, when only that function is relevant. FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD3 AVDD2 AIN1 AIN1 AIN2 AIN2 AIN3 AIN3 AIN4 AIN4 PROGRAMMABLE GAIN DECIMATOR/HPF DC CALIBRATION SERIAL AUDIO PORT AVDDx ADC ADC ADC ADC 3.3V TO 1.8V REGULATOR BG REF AGNDx AVDDx AGNDx AGNDx...