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ADFS7124-8 - 8-Channel 24-Bit Sigma-Delta ADC

Description

Specifications 4 Timing Characteristics10 Absolute Maximum Ratings 13 Thermal Resistance 13 ESD Caution13 Pin Configuration and Function Descriptions 14 Typical Performance Characteristics 17 Terminology 26 RMS Noise and Resolution 27 Full Power Mode 27 Mid Power Mode 30 Low Power Mode33 Getting S

Features

  • Functional safety approved to SC3 by TÜV Rheinland, File Number 968/FSP 2188.01/23.
  • Three power modes.
  • RMS noise.
  • Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 µA typical).
  • Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 µA typical).
  • Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 µA typical).
  • Up to 22 noise free bits in all power modes (gain = 1).
  • Output data rate.
  • Full power: 9.38 SPS to 19,200 SPS.
  • Mid power: 2.34 SPS to 4800 SPS.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Data Sheet ADFS7124-8 8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference FEATURES ► Functional safety approved to SC3 by TÜV Rheinland, File Number 968/FSP 2188.01/23 ► Three power modes ► RMS noise ► Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 µA typical) ► Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 µA typical) ► Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 µA typical) ► Up to 22 noise free bits in all power modes (gain = 1) ► Output data rate ► Full power: 9.38 SPS to 19,200 SPS ► Mid power: 2.34 SPS to 4800 SPS ► Low power: 1.
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